The present disclosure relates generally to semiconductor devices, and more particularly, to a pad structure for backside illuminated image sensors and methods of forming same.
Image sensors provide a grid of pixels, such as photosensitive diodes or photodiodes, reset transistors, source follower transistors, pinned layer photodiodes, and/or transfer transistors, for recording an intensity or brightness of light. The pixel responds to the light by accumulating charge carriers (such as electrons and/or holes) generated when the light passes into/through a silicon layer. The more light, the more charge carriers are generated. The charge carriers are picked-up by sensors and converted into an electric signal subsequently usable by other circuits to provide color and brightness information for suitable applications, such as digital cameras. Common types of pixel grids include a charge-coupled device (CCD) or complementary metal oxide semiconductor (CMOS) image sensor (CIS) formed on a silicon semiconductor die. A semiconductor chip, when incorporated in an electronic circuit, communicates with the outside world through various input/output (I/O) pads, such as signal pads, and power/ground (P/G) pads.
FIG. 1 is a cross-sectional view of an image sensor device 100 comprising a substrate 102 sandwiched between glass layers 108 and 112. Glass layer 108 protectively covers pixel array 104, optical and filter elements 160 and an application-specific integrated circuit (ASIC) 106 formed on a semiconductor device substrate 150. A gap 151 separates the glass layer 108 from pixel array substrate 150 and optical and filter elements 160. A compositional layer 110 comprising metal multi-layer interconnect (MLI) layers M1-M3 is formed on the substrate 150. Each MLI comprises a layer containing metal traces that electrically connect portions of an MLI to another MLI. The metal traces are separated by a dielectric material 117 which is also used to form via layers between the layers containing the metal traces. The via layers have metal vias 116 that electrically connect metal traces in different layers. An electric conductor or metal layer 119 provides an I/O interface to off chip circuitry through a side connected T-connect pad (not shown). T-connect pads connect to pad portions 120 formed in metal layer 119 formed at the edge of image sensor device 100. The pad portions 120 are separated from other pad portions 120 by dielectric material 117. Further, because the connection is made on the side of image sensor device pad portions 120 are formed at the edge of the metal layer 119, under integrated circuit (ASIC) 106, but not formed under pixel array 104.
The image sensor device 100 of FIG. 1 is fabricated using Chip Scale Packaging (CSP) to reduce the size of the device. The fabrication process includes depositing an electric conductor over the entire substrate 102. Any excess conductor is removed by planarizing the substrate 102 by, for example, a chemical-mechanical polishing (CMP) process to form pad portions 120. However, CMP is a well-known cause of low yield in the fabrication of metallic, e.g., Copper (Cu) layer 119, due to fabrication problems including dielectric erosion and metal dishing effects that might occur within a metallic surface having a large line width, thereby reducing the thickness of the Cu layer 119 and thus increasing the electrical resistance of an interconnection with external circuitry.
FIG. 2 illustrates a top view of metal layer 119 in which slits or areas 122 of dielectric material 117 are formed in through holes in the metal layer to prevent dishing, i.e., the formation of depressions or concave portions of the metal layer as a result of CMP, from occurring during CMP. However, as shown by scribe line 109, a cut edge may include a portion of a slit 122 that may provide an inadequate landing surface for a side mounted connector, resulting in poor I/O characteristics because there is very little metal of metal layer 120 exposed at the edge formed by scribe line 109. Accordingly, when forming metal layer 120 with a soft metal, such as Cu, CSP packaging usually requires forming a notch, cut along an angled scribe line 114 in substrate 102, to provide a T-connect pad with sufficient metal contact area to ensure good electrical connectivity with the metal layer.
However, although useful in obviating the problems associated with dishing, the notched slotted metal layer 120 wastes valuable wafer space, i.e., reduces otherwise usable wafer space.